KITSW Main page
Dept. of Electronics & Instrumentation Engg.
KITS Warangal
Faculty group mail-id : eie@kitsw.ac.in
 
Faculty Profile
Address/Contact
Office : Room No. 220, Block - I.
Phone: 0870-2564888(ext:257)
Mobile: 9912155777
E-mail : bj.eie@kitsw.ac.in
 
Education
B.Tech., Electronics & Instrumentation Engg., JNTU, Hyderabad.(2005).
M.Tech., VLSI & Embedded Systems, KAKATIYA UNIVERSITY, Warangal. (2008).
Ph.D., Electronics & Instrumentation Engg.,, KAKATIYA UNIVERSITY, Warangal. (2022).
Dr. B. Jeevan
ASSISTANT PROFESSOR
DEPT. OF ELECTRONICS & INSTRUMENTATION ENGINEERING
Academic Research IDs
Vidwan ID: 179441
SCOPUS ID: 55792313400
Researcher ID: AAD-2064-2022
Google Scholar ID: --
ORCID ID: --
 
ACADEMIC AFFILIATION

Details

FromTo

Name of the Organization

Asst. Professor

June 2008
Till date

 

Kakatiya Institute of Technology & Science, Warangal.

RESEARCH INTERESTS
  • Digital VLSI design
  • VLSI for IoT
  • VLSI Signal Processing
  • SoC Architectures
  • FinFET Technology
PUBLICATIONS
Publications  in Refereed Journals

S. No

Details                                                                                                                                               
1
Jeevan, B., & Sivani, K. (2021). Design of 0.8 V, 22 nm DG-FinFET based efficient VLSI multiplexers. Microelectronics Journal, 113, 105059. (SCI, Impact factor: 1.4) (Elsevier)
2
B.Jeevan, K. Sivani “Heterogeneous Logic: a High Performance and Low Power Non-CMOS 4-1 Multiplexer”, International Journal of Engineering and Advanced Technology (IJEAT), Feb 2020. ISSN: 2249 – 8958.
3
Jeevan, B., & Sivani, K. (2022). A 16 nm finfet circuit with triple function as digital multiplexer, active-high and active-low output decoder for high-performance sram architecture. Semiconductor Science and Technology, 37(8), 085021.(SCI) (IOP Publishing)
4
Battini, J., &Kosaraju, S. (2022). Design of efficient 22 nm, 20-FinFET full adder for low-power and high-speed arithmetic units. Silicon, 1-10.(SCI) (Springer)
Publications in Refereed Conference Proceedings

S.No.
Details

1
B.Jeevan, S,Neeraja, Dr.C.V.Krishna Reddy and Dr. K. Sivani, “Design & Implementation of UART using MODBUS,” in Proc. of International Conference On Electrical, Electronics and Computer Science (ICEECS-2012) on 28th August 2012 at Goa.

2
B.Jeevan, S,Narendar, Dr.C.V.Krishna Reddy and Dr. K. Sivani, “A High Speed Binary Floating Point Multiplier Using Dadda Algorithm,” in Proc. of 2013 IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, iMac4s 2013, Kerala, India, 22nd & 23rd March, 2013 (ISBN NO. 978-1-4673-5088-4).

3
B.Jeevan, C.Nagesh Bhatt, C.V.Krishna Reddy & K.Sivani “ FPGA Implementation of Secure Image Compression 2D-DCT using Verilog HDL,” in Proc. of IEEE International Conference on Devices, Circuits & Systems (ICDCS’14) - Page No. 41-45, 6th  to 8th  March, 2014 at Karunya University, Tamilnadu. ISBN:978-1-4799-1356-5

4
B.Jeevan, K. Sivani, “FPGA Implementation of 64-bit Signed Magnitude Comparator using Verilog HDL,” in Proc. of International Conference on Telecommunication, Power Analysis and Computing Techniques(ICTPACT), April 6-8, 2017. ISSN: 0018-9383.

5
B.Jeevan, K. Sivani,  ” A New High Speed Multiplier based on Carry Look Ahead Adder and Compressor,” in Proc. of IEEE International Conference on Next Gen Electronic Technologies: Silicon to Software, VIT Chennai Campus, India, 23-25, March, 2017. ISSN: 1876-1100
6
B.Jeevan, K. Sivani, “A Review on different logic styles to design High Performance VLSI Decoder.” IEEE International Conference-ICNEWS 2018. BMS College of Engg., Bangalore, December 27th & 28th , 2018. ISSN: 978-1-5386-7949-4.
7
B.Jeevan, Dr. K. Sivani,” A New High Speed Multiplier based on Carry Look Ahead Adder and Compressor”, VLSI Design: Circuits, Systems and Applications,Select Proceedings of ICNETS2, Lecture notes in Electrical Engineering, Springer, Volume 469, ISBN 978-981-10-7250-5, Feb,2018
8
Jeevan, B., Sahithi, P., Samskruthi, P., & Sivani, K. (2022, January). Simulation and synthesis of UART through FPGA Zedboard for IoT applications. In 2022 International Conference on Advances in Computing, Communication and Applied Informatics (ACCAI) (pp. 1-7). IEEE.
9
  • Jeevan, B., Samskruthi, P., Sahithi, P., & Sivani, K. (2022, January). Implementation of parallel multiplier based on Booth computing method using FPGA. In 2022 International Conference on Advances in Computing, Communication and Applied Informatics (ACCAI) (pp. 1-8). IEEE.
10
Jeevan, B., & Sivani, K. (2022, January). Design of 64-bit Signed Magnitude Comparator using FPGA for IoT applications. In 2022 International Conference on Advances in Computing, Communication and Applied Informatics (ACCAI) (pp. 1-5). IEEE.
PROFESSIONAL AFFILIATION

S.No
Details

1
Member – Institute of Electrical and Electronics Engineers (IEEE - 92126392)

2
Member – Indian Society for Technical Education (ISTE- LM 21927)
3
Member – Institution of Electronics and Telecommunication Engineers
COURSES TAUGHT

Undergraduate Level

Courses Taught

Currently Teaching
Course

Semester, Year, Branch
Course

Semester, Year, Branch
Digital Integrated Circuits

II Sem, II/IV, E&I
Digital Design using VHDL

 B.Tech. IV Sem, EIE

Microprocessors & System Interfacing

II Sem, III/IV, CSE
VLSI Design

B.Tech. VI Sem, EIE
Digital Electronics

I Sem, III/IV, CSE
Microprocessors and Interfacing

 B.Tech. VSemester, CSE
Telemetry & Telecontrol

I Sem, IV/IV, E& I.

    
VLSI Design

I Sem, IV/IV, E&I.

    
Computer Architectures and Organization

I Sem, IV/IV B.Tech., E&I

    
Digital Circuits & Logic Design

B.Tech IV Sem CSE

    
Low Power VLSI

M.Tech II Sem, VLSI

    
Micro processors & Micro controllers

I sem, III/IV B.Tech., E&I

    
       

Postgraduate Level
Digital Design

I Sem, M.Tech. VLSI & ES.

 

 
VLSI Technology

I Sem, M.Tech. VLSI & ES.

 

 
Low-Power VLSI

II Sem, M.Tech.VLSI & ES.

   
Digital Design Lab

II Sem, M.Tech.VLSI & ES.

   
       
       
INTERNATIONAL CONFERENCES ATTENDED

S.No.
Details

1
IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, iMac4s 2013 , 22nd & 23rd  March, 2013, Kerala, India.

2
IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, iMac4s 2013, 22nd & 23rd  March, 2013, Kerala, India

3
IEEE International Conference on Telecommunication, Power Analysis and Computing Techniques (ICTPACT), Tamilnadu, April 6-8, 2017.

4
IEEE International Conference on Next Gen Electronic Technologies: Silicon to Software, VIT Chennai Campus, India, 23-25, March, 2017
FACULTY DEVELOPMENT PROGRAMMES/SEMINARS/WORKSHOPS/STTPs ATTENDED

S.No.
Details

1
3-day workshop on “Analog & Mixed signal Design using cadence tools”, JNTU, Hyderabad in association with cadence systems, Bangalore.

2
One Week FDP on “Recent Advances in VLSI”,9th – 14th June, 2014 at Osmania University, Hyderabad

3
One Week FDP on “Digital Communications and FEC Coding Techniques”, 11th -15th , April, 2016 at NIT, Warangal
4
Two week FDP on Computer Networks from 17th-26th June 2016 at NITW, Warangal

5
Two week FDP on Digital VLSI Circuit Design from 3rd-12th June  2017 at NIT, Warangal

6
One Week FDP on Hands on LabVIEW and Its Applications in Engineering from 04.05.2017 to 09.05.2017 at KITS, Warangal

7
Two week FDP on Computer Networks from 17th-26th June 2016 at NITW, Warangal
8
One week AICTE Sponsored STTP on “ VLSI Design: Bridging Concepts to Practise” ( Phase –II) organized by Dept. of EIE, KITSW from 28.12.2020 to 02.01.2021
9
One week AICTE Sponsored STTP on “ Hands on Project based Approach of 5G  Design and Development” ( Phase –III)  organized by Dept. of ECE, KITSW from 18.01.2021 to 23.01.2021
10
A national level One week UGC FDP on “SCI Lab to Engineering Applications” organized by Dept. of ECE, KU from 27.07.2020 to 01.08.2020
11
FDP on “Clock and Data Recovery Circuits” at ECE Dept., NITW. 18.12.2019 to 24.12.2019 (One Week)
12
FDP : A 12-week Online NPTEL course on “ Switching Circuits and Logic Design”2019
13
FDP : A 12-week Online NPTEL course on  NATE.2020
14
Attended one week FDP on "New Pedagogic Techniques in Technical Education", 26th February-3rd March 2018, KITSW and E&ICT
15
A One Week FDP on “Hands on LabVIEW and its applications in Engineering”, 4th -9th May 2017, EIE Dept., KITSW
16
A Two week FDP on “Digital VLSI Circuit Design” from 3rd-12th June  2017, EICT, NITW
OTHER ACTIVITIES

S.No.
Details

1
Acting as Faculty In-charge, Dept. R&D coordinator in KITS Warangal.

2
Acting as I3C cell, Dept. incharge from E&IE, KITS Warangal.

3
Acting as Faculty In-charge for E-CAD Laboratory of Dept. of E&I Engg., KITS, Warangal.
4
Coopted member for BoS, PRR20 (PG) and URR18 (UG) curriculum revision
5
Acting as reviewer for an SCI INDEXED JOURNAL.
6
Acted as co-coordinator for AICTE sponsored STTP in three phases

ARTICLES PUBLISHED IN BOOKS

S.No.
Details

1
B.Jeevan, Dr. K. Sivani,” A New High Speed Multiplier based on Carry Look Ahead Adder and Compressor” ,VLSI Design: Circuits, Systems and Applications,Select Proceedings of ICNETS2, Lecture notes in Electrical Engineering, Springer, Volume 469, ISBN 978-981-10-7250-5, Feb,2018

 
WORKSHOPS / STTPs / FDPs ATTENDED

S.No
Details
1
AICTE Sponsored Two Week Faculty Development Programme (FDP) on “Hands on ProjectBased Approach for Biomedical Signal Analysis using MATLAB” (Phase-1 Online) organized by Department of Electronics and Communication Engineering at Kakatiya Institute of Technology & Science, Warangal, Telangana during 28.12.2020-10.01.2021

2
Two weeks Faculty Development Programme   on “Advances in Internet of Things” organized by  Department of CSE  ,KITS Warangal from 12th to 22nd December 2019

3
NPTEL-AICTE Faculty Development Programme on “Introduction to Research” during Aug – Oct 2019
4
Faculty Development Programme   on “Information Theory and Coding Applications “organized by E&ICT Academy, NIT Warangal, Department of ECE during  21st-26th November,2018
5
Faculty Development Programme   on “Wireless and Mobile Communication” organized by E&ICT Academy, IIT – Guwahati (Venue ‘NIT Warangal) during 21st-26th November,2018
6
  • Faculty Development Programme   on “VLSI DESIGN: BRIDGING CONCEPTS TO PRACTICE” organized by Department of Electronics and Instrumentation Engineering, KITS, Warangal
NPTEL Online Certification “Mathematical Methods and Techniques in Signal Processing” organized by Ministry of HRD, Govt. Of India. during Jan-April 2019

7
  • One week FDP on “New Pedagogic Techniques in Technical Education” organized by TLC-NITW & ETC-KITSW during 26th Feb to 3rd March, 2018
8
“Advances in Wireless Communications Systems” organized by CMR College of Engineering & Technology, Hyd. during 11th to 15th December, 2017

 

 
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